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LOW-POWER ARCHITECTURE FOR CIL-CODE HARDWARE PROCESSOR

Chapyzhenka A. V. and Ragozin D.V. and Umnov A.L. (2005) LOW-POWER ARCHITECTURE FOR CIL-CODE HARDWARE PROCESSOR. Проблеми програмування (4). pp. 20-38. ISSN 1727-4907

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Abstract

In the article the authors present the architecture of a hardware CIL processor, which is capable to execute CIL instructions as native code. The CIL hardware engine is implemented on the top of the low-power DSP architecture, and the CIL processor has two execution cores: DSP and CIL. Such solution allows to execute both CIL and DSP instruction sets as native instructions sets and gain performance in com¬mon multimedia tasks. Therefore, the DSP-based CIL processor may be targeted for multimedia digital home and even embedded applications. The research was sponsored by RFP 2 Microsoft Corp. grant.

Item Type:Article
Subjects:K. Computing Milieux
ID Code:143
Deposited By:G.U. Volkova
Deposited On:25 Apr 2007 17:41
Last Modified:17 Jun 2008 18:03

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